EVAL-AD5443EB【PDF 17/24 页】CAP X7R 470PF 50V 10% 0603

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REV. 0

AD5426/AD5432/AD5443

–17–

Most single-supply circuits include ground as part of the analog

signal range, which in turns requires an amplifier that can handle

rail-to-rail signals, there is a large range of single-supply amplifiers

available from Analog Devices.

MICROPROCESSOR INTERFACING

Microprocessor interfacing to this family of DACs is via a serial bus

that uses standard protocol compatible with microcontrollers and

DSP processors. The communications channel is a 3-wire interface

consisting of a clock signal, a data signal, and a synchronization

signal. The AD5426/AD5432/AD5443 requires a 16-bit word

with the default being data valid on the falling edge of SCLK,

but this is changeable via the control bits in the data-word.

ADSP-21xx to AD5426/AD5432/AD5443 Interface

The ADSP-21xx family of DSPs are easily interface to this family

of DACs without extra glue logic. Figure 13 shows an example of

an SPI interface between the DAC and the ADSP-2191M. SCK

of the DSP drives the serial data line, DIN.

SYNC

is driven from

one of the port lines, in this case

SPIxSEL

SCLK

SCK

AD5426/

AD5432/

AD5443

SYNC

SPIxSEL

SDIN

MOSI

ADSP-2191

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 13. ADSP-2191 SPI to AD5426/AD5432/AD5443

Interface

A serial interface between the DAC and DSP SPORT is shown

in Figure 14. In this interface example, SPORT0 is used to

transfer data to the DAC shift register. Transmission is initiated

by writing a word to the Tx register after the SPORT has been

enabled. In a write sequence, data is clocked out on each rising

edge of the DSPs serial clock and clocked into the DAC input

shift register on the falling edge of its SCLK. The update of the

DAC output takes place on the rising edge of the

SYNC

signal.

SCLK

AD5426/

AD5432/

AD5443

SYNC

TFS

SDIN

ADSP-2101/

ADSP-2103/

ADSP-2191

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 14. ADSP-2101/ADSP-2103/ADSP-2191 SPORT

to AD5426/AD5432/AD5443 Interface

Communication between two devices at a given clock speed is

possible when the following specs are compatible: frame sync delay

and frame sync setup and hold, data delay and data setup and

hold, and SCLK width. The DAC interface expects a t

(

SYNC

falling edge to SCLK falling edge setup time) of 13 ns minimum.

Consult the ADSP-21xx User Manual for information on clock

and frame sync frequencies for the SPORT register.

The SPORT control register should be set up as follows:

TFSW = 1, Alternate Framing

INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

ISCLK = 1, Internal Serial Clock

TFSR = 1, Frame Every Word

ITFS = 1, Internal Framing Signal

SLEN = 1111, 16-Bit Data-Word

80C51/80L51 to AD5426/AD5432/AD5443 Interface

A serial interface between the DAC and the 8051 is shown in

Figure 15. TxD of the 8051 drives SCLK of the DAC serial

interface, while RxD drives the serial data line, D

. P3.3 is a

bit-programmable pin on the serial port and is used to drive

SYNC

. When data is to be transmitted to the switch, P3.3 is

taken low. The 80C51/80L51 transmits data only in 8-bit bytes;

thus, only eight falling clock edges occur in the transmit cycle.

To load data correctly to the DAC, P3.3 is left low after the first

eight bits are transmitted, and a second write cycle is initiated to

transmit the second byte of data. Data on RxD is clocked out of

the microcontroller on the rising edge of TxD and is valid on the

falling edge. As a result, no glue logic is required between the

DAC and microcontroller interface. P3.3 is taken high following

the completion of this cycle. The 8051 provides the LSB of its

SBUF register as the first bit in the data stream. The DAC input

The transmit routine should take this into account.

SCLK

TxD

8051

SYNC

P1.1

SDIN

RxD

AD5426/

AD5432/

AD5443

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 15. 80C51/80L51 to AD5426/AD5432/AD5443

Interface

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